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Frequently Asked Questions

  MicroCore Labs

Q: How small are the MCL51 and MCL86 cores?

A: The MCL86 Execution Unit (EU) core consumes 308 LUTs which is less than one percent of the smallest Kintex-7 FPGA and less than ten percent of the Lattice XO2-7000 FPGA and the MCL51 is 312 Xilinx Artix-7 LUTs. These ultra-small footprints are possible because of the high performance microsequencer that implements all the processor's functionality in microcode.

Q: How do MicroCore Labs cores compare in size to similar processor cores from other vendors?

A: The MCL51 and MCL86 utilize high performance 32-bit microsequencers with all of the target processor's functionality emulated in microcode. This provides an implementation that is less than one tenth the size of competing cores on the market. MicroCore Labs cores have the additional advantage of separating the Execution Units of the CPU from the Bus Interface Units which allows the user to customize peripherals and bus interfaces to their specific designs without having any logic or peripherals that would remain idle.

Q: What peripherals are included with the MCL51?
A: The MCL51 is divided into the Execution Unit and the Bus Interface Unit. The EU contains the microsequencer which emulates the 8051 instruction set and is delivered as encrypted Verilog,  and the BIU contains the SFRs and peripherals and is delivered as source code Verilog. A sample UART which includes an Intel-Hex Loader as well as a dual-channel Timer and an Interrupt controller are provided with the MCL51 which are proxy addressable rather than integrated with the SFRs as with the original 8051. Having a separate BIU allows the user to add highly customized peripherals to their designs.


Q: What is the interface to the MCL86 core?

A:  The MCL86 Execution Unit (EU) has a 16-bit interface to the Bus Interface Unit (BIU). Like the original 8086 and 8088, the MCL86 EU and the BIU are separate units which allows the user to connect any type of BIU to the MCL86 core. An 8088 compatible BIU and a minimal "system on a chip" BIU are both provided as examples with the core.

Q: Can I use the MCL86 core and the example BIU as a drop-in replacement for an original 8088?
A:  Yes. This is actually the way we implemented and tested the core's functionality. The example BIU has a 4-byte prefetch queue and an 8-bit multiplexed data bus operating in "Maximum Mode" like the original 8088. Alternatively, a 16-bit 8086 BIU can easily be developed, or any other interface that the user requires.

Q: If don't need cycle or bus compatibility, can I run the MCL86 core faster or have a wider bus than the original x86?

A:   Yes. The user can easily disable the cycle compatibility to save the space and increase the core's performance. The core can be run at any clock speed from DC to the maximum that the FPGA allows. The core only needs to run at 100Mhz when cycle compatibility is required.

Q: What tools can I use to develop code for 16-bit instruction set?
A: For assembly we have verified  A86 (DOSBox),  MASM (DOSBox),  NASM (Linux/Windows 7),  as86 (Linux), emu8086 (Windows 7) and for C/C++ we have tested Open Watcom (Windows 7),  bcc (Linux).   There are many more tools available, but these are ones we have recently tried on Windows 7 and Linux.

Q: Can I run debuggers on the MCL86 core?
A: Yes. The MCL86 core supports single stepping and interrupts the same way as the original 8086 and 8088. Please see our Links page for video demonstrations of the core running  a few desktop debuggers.

Q: Are undocumented and unused x86 instructions supported?
A:  Yes. Undocumented instructions and redundant opcodes such as SETALC are supported.

Q: In what ways can the BIU size be enhanced, reduced or optimized?
A:  The example 8088 BIU has an 8-bit local bus, a four byte prefetch queue and supports all  bus modes. Any of these can be modified by the user. If, for example,  if all software is memory mapped then support for IO reads and writes can be optimized out of the BIU. The prefetch queue can also be increased or decreased in depth if desired. Increasing the local bus width to 16 or 32 bits is easy to do as well. The minimal example BIU which is also provided with the core is a system-on-a-chip with the MCL86 EU core, RAM, ROM, and a UART residing in a Lattice XO2 FPGA.

Q: Is the core detected by software as an 8088 or a V20 processor?
A: The microcode is written to indicate that this core is a genuine 8088.